1. Field of the Invention
The present invention relates generally to an apparatus for testing electronic devices such as IC memory devices. More particularly, the invention is concerned with a circuit for connecting sequentially a plurality of devices under test to a single measuring apparatus or a tester. The present invention can profitably be applied to the test of integrated circuit (IC) memory devices by resorting to a directed current or DC measurement.
2. Description of the Prior Art
For having a better understanding of the present invention, description will first be made of a structure of the prior art circuit by reference to FIG. 3 of the accompanying drawings.
In FIG. 3, a reference symbol 1A denotes an oscillator, 1B denotes a start flip-flop circuit, 1C denotes a NOR circuit, 1D denotes a stop flip-flop circuit, 1E denotes a NOR circuit, 1F denotes a pin-end flag flip-flop circuit, 1G denotes a scanning counter, 2A to 2D denote, respectively, ROMs (read-only memories) for binary coded decimal conversion, 3A to 3D denotes registers, respectively, 4A to 4D denote NOR circuits, respectively, 7 denotes a DC measuring apparatus, 8A to 8D denote pin cards, respectively, 9A to 9D denote, respectively, devices under test (also referred to as the device to be tested or DUT in abbreviation), 10A to 10D denote inverter circuits, respectively, and finally a reference numeral 11 denotes an OR circuit.
In the case of the example shown in FIG. 3, it is assumed that each of the devices under test or DUTs 9A to 9D is provided with 32 pins, wherein the pins for measurement of the DUTs 9A to 9D are classified into four groups, as mentioned below.
For the DUT 9A, 1st to 32nd pins.
For the DUT 9B, 33rd to 64th pins.
For the DUT 9C, 65th to 96th pins.
For the DUT 9D, 97th to 128th pins.
Pin data for the measurement of the DUTs which are transferred from a central processing unit or CPU (not shown) are stored in the registers 3A to 3D, respectively, in such a manner as mentioned below.
(a) Data of the 1st to 8th pins used for the test or measurement of the DUT 9A are stored in the register 3A.
(b) Data of the 33rd to 40th pins for the measurement of the DUT 9B are stored in the register 3B.
(c) Data of the 65th to 72nd pins for the measurement of the DUT 9C are stored in the register 3C.
(d) Data of the 97th to 104th pins for the measurement of the DUT 9D are stored in the register 3D.
The ROMs 2A to 2D are loaded with data for the binary conversion or BCD conversion.
Operation for measuring or testing the DUTs is usually carried out in a manner described below.
At first, a start signal is supplied from the central processing unit or CPU. In response thereto, the start flip-flop circuit 1B is set, whereon the scanning counter 1G is activated to start counting the pulses generated by the oscillation circuit 1A.
The binary coded decimal conversion (BCD) ROMs 2A to 2D generate output scanning data for the 1st to 128th pins in response to the outputs of the scanning counter 1G, respectively. Assuming now that the scanning data is for the 1st pin, coincidence is then found with the output data of the register 3A, whereby the stop flip-flop circuit 1D is set through the NOR circuit 4A and the OR circuit 11, as a result of which the start flip-flop circuit 1D is reset. Thus, the scanning counter 1G is caused to stop the counting operation temporarily. In this state, an associated relay incorporated in the pin card 8A is turned on, resulting in that the device under test or DUT 9A is connected to the DC measuring apparatus 7 which then starts the measurement of a direct current or DC. Upon completion of the measurement performed by the DC measuring apparatus 7, the scanning counter 1G again starts the counting operation in response to the start signal 21 supplied from the CPU. In this manner, measurement is performed sequentially for the 2nd to 8th pins through the similar processes.
In succession to completion of the abovementioned measurement, the scanning counter 1G starts once again the counting operation for the measurement via the 9th to 32nd pins in response to the start signal 21 supplied from the CPU. At this time, however, the registers 3A to 3D store no data for the 9th to 32nd pins, as mentioned hereinbefore in conjunction with the distributed data storage among the registers 3A to 3D. Consequently, no coincidence is established with the scanning data held in the binary coded decimal (BCD) conversion ROMs 2A to 2D, which results in that the scanning counter 1G proceeds up to the 33rd pin to stop thereat temporarily for performing the measurement via that pin.
In this manner, on the assumption made hereinbefore in conjunction with the distributed data storage among the registers 3A to 3D, measurements can be subsequently performed via the 34th to 40th pins, 65th to 72nd pins and the 97th to 104th pins, respectively.
For the 105th to 128th pins, no scanning data are contained in the registers 3A to 3D on the assumption made hereinbefore. Consequently, the scanning counter 1G continues the counting operation until a carry is generated, whereupon the pin-end flag flip-flop circuit 1F is set with the scanning counter 1G stopping the counting operation, while a pin-end flag 22 is set. The CPU detects the pin-end flag to recognize that the measurement has been completed for all the pins. Thus, the whole test or measurement sequence comes to an end.